In-depth analysis of x86 instruction set condition codes influence on superscalar execution

Instruction set design is a crucial aspect of computer architecture. The requirements to fulfill have evolved along time. For superscalar processing the most important feature is to avoid code coupling caused by data dependencies. However, instruction sets may have particular characteristics that produce a negative impact into the amount of available parallelism for which it is important to analyze them. The popular x86 instruction set architecture includes some of those characteristics that may have negative effects in superscalar processing that may influence the final performance: dedicated use of registers, implicit operands, complex effective address computation mechanisms, condition codes usage, etc. It is therefore, an ideal candidate to use for evaluation purposes. Specifically, we analyze the impact produced by condition codes. In this work we take two approaches to solve the problem. On the first one we perform a statistical analysis of the utilization of instructions and operands. On the second we perform a mathematical analysis based on graph theory that provides a quantification for the contribution due to condition codes to the overall coupling according to the different dependence types. Finally, we evaluate the influence of condition codes utilization into the microperation level, proposing some solutions to achieve an improvement in performance.